This invention relates generally to logic level translators and more particularly, it relates to a logic translator having a fast rising edge which is used to interface between an emitter-coupled-logic (ECL) input stage and a transistor-transistor-logic (TTL) output stage.
Heretofore, computer data processing systems utilize various types of logic in different parts of the processing system. In order to transfer data from one part of the processing system to another part, there is often required a translation from one type of logic to another type of logic. Since many of these processing systems are designed wtih both ECL and TTL logic circuits, there has been encountered a need for interface circuits such as ECL-to-TTL and TTl-to-ECL translators so that these types of logic circuits will be compatible with each other.
As is generally known in the art, TTL logic circuits typically operate on logic signal levels below 0.3 volts and above 3.5 volts and ECL logic circuits typically operate on different logic signal levels. While the precise levels utilized in the ECL logic circuits differ among manufacturers, the voltage swing between the two ECL logic levels is commonly less than the voltage swing between two TTL logic levels. Thus, in order to shift or convert ECL logic level signals to TTL logic level signals, it can be seen that that smaller ECL input swing must result in a larger TTL output swing. One of the major problems experienced is that these level translator circuits tend to cause too large of a propagation delay in transmitting data from the input to the output. In other words, the response time is relatively slow during switching between the low and high output logic levels.
A logic level translator of the prior art is shown in FIG. 1 and has been labeled "Prior Art". The prior art translator 10 is interconnected between an ECL input stage 12 and a TTL output stage 14. The logic level translator of the present invention is an improvement over the translator circuit of FIG. 1 which exhibits a faster rising edge at the input to the TTL output stage 14. The propagation delay during a high-to-low output transition at such output stage of the present level translator is reduced by approximately 2 nanoseconds over the translator circuit of FIG. 1.